1. Field
Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a method of forming a gate dielectric layer and a method of fabricating a semiconductor device using the same.
2. Description of the Related Art
To accommodate high integration of a semiconductor device, the thickness of a gate dielectric layer is being decreased for transistors. Here, when the thickness of the gate dielectric layer is reduced, leakage current increases. To address such features, a gate dielectric layer with a dielectric constant higher than a silicon oxide has been developed. When a gate dielectric layer is said to have high dielectric constant (high-k), it indicates a dielectric material with a dielectric constant greater than 4 (for example, 7). The high-k gate dielectric layer may have excellent thermal stability at a high temperature and may suppress leakage current.
According to an exemplary method, when fabricating a PMOSFET (hereinafter, referred to as a ‘PMOS’) using a high-k gate dielectric layer, a capping layer such as alumina (Al2O3) is used between the high-k gate dielectric layer and a gate electrode to control a threshold voltage (Vt) variation. However, in the case of applying the capping layer such as alumina, as a threshold voltage variation increases, degradation of mobility occurs, and thus, it is difficult to secure a threshold voltage of a desired level.